View 723622L12PQF_3889856.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 2001 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. dsc-3022/4 ? december 2001 cmos syncbififo tm 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 idt723622 idt723632 idt723642 idt and the idt logo are trademarks of integrated device technology, inc. syncbififo is a trademark of integrated device techn ology, inc. commercial temperature range features: ? ? ? ? ? memory storage capacity: idt723622 ? 256 x 36 x 2 idt723632 ? 512 x 36 x 2 idt723642 ? 1,024 x 36 x 2 ? ? ? ? ? free-running clka and clkb may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) ? ? ? ? ? two independent clocked fifos buffering data in opposite directions ? ? ? ? ? mailbox bypass register for each fifo ? ? ? ? ? programmable almost-full and almost-empty flags ? ? ? ? ? microprocessor interface control logic ? ? ? ? ? ira, ora, aea , and afa flags synchronized by clka ? ? ? ? ? irb, orb, aeb , and afb flags synchronized by clkb ? ? ? ? ? supports clock frequencies up to 83mhz ? ? ? ? ? fast access times of 8ns ? ? ? ? ? available in 132-pin plastic quad flatpack (pqfp) or space- saving 120-pin thin quad flatpack (tqfp) ? ? ? ? ? low-power 0.8-micron advanced cmos technology ? ? ? ? ? industrial temperature range (?40 c to +85 c) is available description: the idt723622/723632/723642 are a monolithic, high-speed, low-power, cmos bidirectional syncfifo (clocked) memory which supports clock fre- quencies up to 83mhz and have read access times as fast as 8ns. two independent 256/512/1,024 x 36 dual-port sram fifos on board each chip buffer data in opposite directions. communication between each port may bypass the fifos via two 36-bit mailbox registers. each mailbox register has a flag to signal when new mail has been stored. these devices are a synchronous (clocked) fifo, meaning each port employs a synchronous interface. all data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. the clocks for each port are independent of one another and can be asynchronous or mail 1 register programmable flag offset registers input register output register ram array 256 x 36 512 x 36 1,024 x 36 write pointer read pointer status flag logic input register output register ram array 256 x 36 512 x 36 1,024 x 36 write pointer read pointer status flag logic clka csa w/ r a ena mba port-a control logic fifo1, mail1 reset logic rst1 mail 2 register mbf2 clkb csb w /rb enb mbb port-b control logic fifo2, mail2 reset logic rst2 mbf1 fifo 1 fifo 2 10 orb aeb 36 36 irb afb b 0 - b 35 ira afa fs 0 fs 1 a 0 - a 35 ora aea 3022 drw 01 36 36 functional block diagram
2 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range description (continued) notes: 1. nc ? no internal connection 2. uses yamaichi socket ic51-1324-828 pin configuration pqfp (pq132-1, order code: pqf) top view nc nc a 35 a 34 a 33 a 32 v cc a 31 a 30 gnd a 29 a 28 a 27 a 26 a 25 a 24 a 23 gnd a 22 v cc a 21 a 20 a 19 a 18 gnd a 17 a 16 a 15 a 14 a 13 v cc a 12 nc nc b 35 b 34 b 33 b 32 gnd b 31 b 30 b 29 b 28 b 27 b 26 v cc b 25 b 24 gnd b 23 b 22 b 21 b 20 b 19 b 18 gnd b 17 b 16 v cc b 15 b 14 b 13 b 12 gnd nc nc 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 3022 drw 02 nc nc nc v cc clkb enb w /rb csb gnd irb orb afb aeb v cc mbf1 mbb rst2 fs1 gnd fs0 rst1 mba mbf2 aea afa v cc ora ira csa w/ r a ena clka gnd 117 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 nc nc b 11 b 10 b 9 b 7 b 8 v cc b 6 gnd b 5 b 4 b 3 b 2 b 1 b 0 gnd a 0 a 1 a 2 v cc a 3 a 4 a 5 gnd a 6 a 7 a 8 a 9 a 10 a 11 gnd nc 74 76 77 78 79 80 81 82 83 75 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 coincident. the enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchro- nous control. each fifo has a programmable almost-empty flag ( aea and aeb ) and a progammable almost-full flag ( afa and afb ). aea and aeb indicate when a selected number of words remain in the fifo memory. afa and afb indicate when the fifo contains more than a selected number of words. the input ready (ira, irb) and almost-full ( afa , afb ) flags of a fifo are two-stage synchronized to the port clock that writes data into its array. the output ready (ora, orb) and almost-empty ( aea , aeb ) flags of a fifo are two-stage synchronized to the port clock that reads data from its array. offset values for the almost-full and almost-empty flags of both fifos can be programmed from port a. two or more devices may be used in parallel to create wider data paths. if, at any time, the fifo is not actively performing a function, the chip will automatically power down. during the power down state, supply current consumption (i cc ) is at a minimum. initiating any operation (by activating control inputs will immediately take the device out of the power down state. the 723622/723632/723642 are characterized for operation from 0 c to 70 c. industrial temperature range (-40 c to +85 c) is available by special order. they are fabricated using idt's high speed, submicron cmos technology.
3 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range pin configuration (continued) tqfp (pn120-1, order code: pf) top view 3022 drw 03 a 35 a 34 a 33 a 32 v cc a 31 a 30 gnd a 29 a 28 a 27 a 26 a 25 a 24 a 23 gnd a 22 v cc a 21 a 20 a 19 a 18 gnd a 17 a 16 a 15 a 14 a 13 v cc a 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 b 35 b 34 b 33 b 32 gnd b 31 b 30 b 29 b 28 b 27 b 26 v cc b 25 b 24 gnd b 23 b 22 b 21 b 20 b 19 b 18 gnd b 17 b 16 v cc b 15 b 14 b 13 b 12 gnd 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 91 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 v cc gnd clka ena w/ r a csa ira ora v cc afa aea mbf2 mba rst1 fs0 gnd fs1 rst2 mbb mbf1 v cc aeb afb orb irb gnd csb w /rb enb clkb gnd a 11 a 10 a 9 a 8 a 7 a 6 gnd a 5 a 4 a 3 v cc a 2 a 1 a 0 gnd b 0 b 1 b 2 b 3 b 4 b 5 gnd b 6 v cc b 7 b 8 b 9 b 10 b 11 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
4 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range pin descriptions symbol name i/o description a0-a35 port a data i/0 36-bit bidirectional data port for side a. aea port a almost- o programmable almost-empty flag synchronized to clka. it is low when the number of words empty flag (port a) in fifo2 is less than or equal to the value in the almost-empty a offset register, x2. aeb port b almost- o programmable almost-empty flag synchronized to clkb. it is low when the number of words empty flag (port b) in fifo1 is less than or equal to the value in the almost-empty b offset register, x1. afa port a almost- o programmable almost-full flag synchronized to clka. it is low when the number of empty full flag (port a) locations in fifo1 is less than or equal to the value in the almost-full a offset register, y1. afb port b almost- o programmable almost-full flag synchronized to clkb. it is low when the number of empty full flag (port b) locations in fifo2 is less than or equal to the value in the almost-full b offset register, y2. b0 - b35 port b data i/o 36-bit bidirectional data port for side b. clka port a clock i clka is a continuous clock that synchronizes all data transfers through port a and can be asynchronous or coincident to clkb. ira, ora, afa , and aea are all synchronized to the low-to-high transition of clka. clkb port b clock i clkb is a continuous clock that synchronizes all data transfers through port b and can be asynchronous or coincident to clka. irb, orb, afb , and aeb are synchronized to the low- to-high transition of clkb. csa port a chip i csa must be low to enable a low-to-high transition of clka to read or write on port a. select the a0-a35 outputs are in the high-impedance state when csa is high. csb port b chip i csb must be low to enable a low-to-high transition of clkb to read or write data on select port b. the b0-b35 outputs are in the high-impedance state when csb is high. ena port a enable i ena must be high to enable a low-to-high transition of clka to read or write data on port a. enb port b enable i enb must be high to enable a low-to-high transition of clkb to read or write data on port b. fs1, fs0 flag offset i the low-to-high transition of a flfo?s reset input latches the values of fs0 and fs1. selects if either fs0 or fs1 is high when a reset goes high, one of three preset values is selected as the offset for the flfos almost-full and almost-empty flags. if both fifos are reset simultaneously and both fs0 and fs1 are low when rst1 and rst2 go high, the first four writes to fifo1 load the almost-empty and almost-full offsets for both flfos. ira input ready o ira is synchronized to the low-to-high transition of clka. when ira is low, fifo1 is full flag (port a) and writes to its array are disabled. ira is set low when fifo1 is reset and is set high on the second low-to-high transition of clka after reset. irb input ready o irb is synchronized to the low-to-high transition of clkb. when irb is low, fifo2 is full flag (port b) and writes to its array are disabled. irb is set low when fifo2 is reset and is set high on the second low-to-high transition of clkb after reset. mba port a mailbox i a high level on mba chooses a mailbox register for a port a read or write operation. select when the a0-a35 outputs are active, a high level on mba selects data from the mail2 register for output and a low level selects fifo2 output register data for output. mbb port b mailbox i a high level on mbb chooses a mailbox register for a port b read or write operation. when the select b0-b35 outputs are active, a high level on mbb selects data from the mail1 register or output and a low level selects fifo1 output register data for output. mbf1 mail1 register o mbf1 is set low by a low-to-high transition of clka that writes data to the mail1 flag register. writes to the mail1 register are inhibited while mbf1 is low. mbf1 is set high by a low-to-high transition of clkb when a port b read is selected and mbb is high. mbf1 is set high when fifo1 is reset. mbf2 mail2 register o mbf2 is set low by a low-to-high transition of clkb that writes data to the mail2 register. flag writes to the mail2 register are inhibited while mbf2 is low. mbf2 is set high by a low- to-high transition of clka when a port a read is selected and mba is high. mbf2 is also set high when fifo2 is reset.
5 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range symbol name i/o description ora output ready o ora is synchronized to the low-to-high transition of clka. when ora is low, fifo2 is flag (port a) empty and reads from its memory are disabled. ready data is present on the output register of fifo2 when ora is high. ora is forced low when flfo2 is reset and goes high on the third low-to-high transition of clka after a word is loaded to empty memory. orb output ready o orb is synchronized to the low-to-high transition of clkb. when orb is low, flfo1 is flag (port b) empty and reads from its memory are disabled. ready data is present on the output register of fifo1 when orb is high. orb is forced low when fifo1 is reset and goes high on the third low-to- high transition of clkb after a word is loaded to empty memory. rst1 fifo1 reset i to reset fifo1, four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while rst1 is low. the low-to-high transition of rst1 latches the status of fs0 and fs1 for afa and aeb offset selection. fifo1 must be reset upon power up before data is written to its ram. rst2 fifo2 reset i to reset fifo2, four low-to-high transitions of clka and four low-to-high transitions of clkb must occur while rst2 is low. the low-to-high transition of rst2 latches the status of fs0 and fs1 for afb and aea offset selection. fifo2 must be reset upon power up before data is written to its ram. w/ r a port a write/ i a high selects a write operation and a low selects a read operation on port a for a low-to-high read select transition of clka. the a0-a35 outputs are in the high impedance state when w/ r a is high. w /rb port b write/ i a low selects a write operation and a high selects a read operation on port b for a low-to-high read select transition of clkb. the b0-b35 outputs are in the high-impedance state when w /rb is low. pin descriptions (continued)
6 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range notes: 1. industrial temperature range product is available by special order. 2. all typical values are at v cc = 5v, t a = 25 c. 3. for additional i cc information, see figure 1, typical characteristics: supply current (i cc ) vs. clock frequency (f s ) . 4. characterized values, not currently tested. electrical characteristics over recommended operating free- air temperature range (unless otherwise noted) idt723622 idt723632 idt723642 commercial t clk = 12, 15 ns symbol parameter test condit ions min. typ. (2) max. unit v oh output logic "1" voltage v cc = 4.5v, i oh = ?4 ma 2.4 ? ? v v ol output logic "0" voltage v cc = 4.5v, i ol = 8 ma ? ? 0.5 v i li input leakage current (any input) v cc = 5.5v, v i = v cc or 0 ? ? 10 a i lo output leakage current v cc = 5.5v, v o = v cc or 0 ? ? 10 a i cc2 (3) standby current (with clka & clkb running) v cc = 5.5v, v i = v cc ?0.2v or 0v ? ? 8 ma i cc3 (3) standby current (no clocks running) v cc = 5.5v, v i = v cc ?0.2v or 0v ? ? 1 ma c in (4) input capacitance v i = 0, f = 1 mhz ? 4 ? pf c out (4) output capacitance v o = 0, f = 1 mhz ? 8 ? pf recommended operating conditions symbol parameter min. typ. max. unit v cc supply voltage (commercial) 4.5 5.0 5.5 v v ih high-level input voltage (commercial) 2 ? ? v v il low-level input voltage (commercial) ? ? 0.8 v i oh high-level output current (commercial) ? ? ?4 ma i ol low-level output current (commercial) ? ? 8 ma t a operating temperature (commercial) 0 ? 70 c absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) symbol rating commercial unit v cc supply voltage range ?0.5 to 7 v v i (2) input voltage range ?0.5 to v cc +0.5 v v o (2) output voltage range ?0.5 to v cc +0.5 v i ik input clamp current (v i < 0 or v i > v cc ) 20 ma i ok output clamp current (v o = < 0 or v o > v cc ) 50 ma i out continuous output current (v o = 0 to v cc ) 50 ma i cc continuous current through v cc or gnd 400 ma t stg storage temperature range ?65 to 150 c notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress rat ings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute m aximum rated conditions for extended periods may affect device reliability. 2. the input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
7 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range determining active current consumption and power dissipation the i cc(f) current for the graph in figure 1 was taken while simultaneously reading and writing a fifo on the idt723622/723632/723642 wit h clka and clkb set to f s . all data inputs and data outputs change state during each clock cycle to consume the highest supply current. data outputs w ere disconnected to normalize the graph to a zero capacitance load. once the capacitance load per data-output channel and the numb er of these device's inputs driven by ttl high levels are known, the power dissipation can be calculated with the equation below. calculating power dissipation with i cc(f) taken from figure 1, the maximum power dissipation (p t ) of these fifos may be calculated by: p t = v cc x [i cc (f) + (n x ? i cc x dc)] + (c l x v cc 2 x fo) where: n = number of outputs = 36 ? i cc = increase in power supply current for each input at a ttl high level dc = duty cycle of inputs at a ttl high level of 3.4 v c l = output capacitance load fo = switching frequency of an output figure 1. typical characteristics: supply current (i cc ) vs clock frequency (f s ) 010 20 30 40 50 60 70 0 50 100 250 300 v cc = 5.0v f s ? clock frequency ? mhz f data = 1/2 f s t a = 25 c c l = 0pf v cc = 5.5v 3022 drw 03a 200 150 v cc = 4.5v 80 90 i cc(f) supply current ma
8 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range commercial idt723622l12 idt723622l15 idt723632l12 idt723632l15 idt723642l12 idt723642l15 symbol parameter min. max. min. max. unit f s clock frequency, clka or clkb ? 83 ? 66.7 mhz t clk clock cycle time, clka or clkb 12 ? 15 ? ns t clkh pulse duration, clka or clkb high 5 ? 6 ? ns t clkl pulse duration, clka and clkb low 5 ? 6 ? ns t ds setup time, a0-a35 before clka and b0-b35 before clkb 3?4?ns t ens1 setup time, csa and w/ r a before clka ; csb and w /rb before clkb 4 ? 4.5 ? ns t ens2 setup time, ena and mba, before clka ; enb and mbb before clkb 3 ? 4.5 ? ns t rsts setup time, rst1 or rst2 low before clka or clkb (2) 5?5?ns t fss setup time, fs0 and fs1 before rst1 and rst2 high 7.5 ? 7.5 ? ns t dh hold time, a0-a35 after clka and b0-b35 after clkb 0.5 ? 1 ? ns t enh hold time, csa , w/ r a, ena, and mba after clka ; csb , w /rb, enb, 0.5 ? 1 ? ns and mbb after clkb t rsth hold time, rst1 or rst2 low after clka or clkb (2) 4?4?ns t fsh hold time, fs0 and fs1 after rst1 and rst2 high 2 ? 2 ? ns t skew1 (3) skew time, between clka and clkb for ora, orb, ira, and irb 7.5 ? 7.5 ? ns t skew2 (3,4) skew time, between clka and clkb for aea , aeb , afa , and afb 12 ? 12 ? ns notes: 1. industrial temperature range product is available by special order. 2. requirement to count the clock edge as one of at least four needed to reset a fifo. 3. skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship b etween clka cycle and clkb cycle. 4. design simulated, not tested. timing requirements over recommended ranges of supply voltage and operating free-air temperature (commercial: v cc = 5v 10%, t a = 0 c to +70 c)
9 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range notes: 1. industrial temperature range product is available by special order. 2. writing data to the mail1 register when the b0-b35 outputs are active and mbb is high. 3. writing data to the mail2 register when the a0-a35 outputs are active and mba is high. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, cl = 30 pf (commercial: v cc = 5v 10%, t a = 0 c to +70 c) commercial idt723622l12 idt723622l15 idt723632l12 idt723632l15 idt723642l12 idt723642l15 symbol parameter min. max. min. max. unit t a access time, clka to a0-a35 and clkb to b0-b35 2 8 2 10 ns t pir propagation delay time, clka to ira and clkb to irb 2 8 2 8 ns t por propagation delay time, clka to ora and clkb to orb 1 8 1 8 ns t pae propagation delay time, clka to aea and clkb to aeb 1818ns t paf propagation delay time, clka to afa and clkb to afb 1818ns t pmf propagation delay time, clka to mbf1 low or mbf2 high and 0 8 0 8 ns clkb to mbf2 low or mbf1 high t pmr propagation delay time, clka to b0-b35 (2) and clkb to a0-a35 (3) 28210ns t mdv propagation delay time, mba to a0-a35 valid and mbb to b0-b35 valid 2 8 2 10 ns t rsf propagation delay time, rst1 low to aeb low, afa high, and 1 10 1 15 ns mbf1 high, and rst2 low to aea low, afb high, and mbf2 high t en enable time, csa and w/ r a low to a0-a35 active and csb low 2 6 2 10 ns and w /rb high to b0-b35 active t dis disable time, csa or w/ r a high to a0-a35 at high-impedance and 1 6 1 8 ns csb high or w /rb low to b0-b35 at high-impedance
10 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range ? parallel load from port a to program the x1, x2, y1, and y2 registers from port a, both flfos should be reset simultaneously with fs0 and fs1 low during the low-to-high transition of the reset inputs. after this reset is complete, the first four writes to fifo1 do not store data in the fifo memory but load the offset registers in the order y1, x1, y2, x2. the port a data inputs used by the offset registers are (a7-a0), (a8-a0), or (a9-a0) for the idt723622, idt723632, or idt723642, respectively. the highest numbered input is used as the most significant bit of the binary number in each case. valid programming values for the registers ranges from 1 to 252 for the idt723622; 1 to 508 for the idt723632; and 1 to 1,020 for the idt723642. after all the offset registers are programmed from port a, the port b input ready flag (irb) is set high, and both fifos begin normal operation. see figure 3 for relevant offset register parallel programming timing diagram. fifo write/read operation the state of the port a data (a0-a35) outputs is controlled by port a chip select ( csa ) and port a write/read select (w/ r a). the a0-a35 outputs are in the high-impedance state when either csa or w/ r a is high. the a0-a35 outputs are active when both csa and w/ r a are low. data is loaded into fifo1 from the a0-a35 inputs on a low-to-high transition of clka when csa is low, w/ r a is high, ena is high , mba is low, and ira is high. data is read from fifo2 to the a0-a35 outputs by a low-to-high transition of clka when csa is low, w/ r a is low, ena is high, mba is low, and ora is high (see table 2). fifo reads and writes on port a are independent of any concurrent port b operation. write and read cycle timing diagrams for port a can be found in figure 4 and 7. the port b control signals are identical to those of port a with the exception that the port b write/read select ( w /rb) is the inverse of the port a write/read select (w/ r a). the state of the port b data (b0-b35) outputs is controlled by the port b chip select ( csb ) and port b write/read select ( w /rb). the b0-b35 outputs are in the high-impedance state when either csb is high or w /rb is low. the b0-b35 outputs are active when csb is low and w /rb is high. data is loaded into fifo2 from the b0-b35 inputs on a low-to-high transition of clkb when csb is low, w /rb is low, enb is high, mbb is low, and irb is high. data is read from fifo1 to the b0-b35 outputs by a low- to-high transition of clkb when csb is low, w /rb is high, enb is high, mbb is low, and orb is high (see table 3) . fifo reads and writes on port b are independent of any concurrent port a operation. write and read cycle timing diagrams for port b can be found in figure 5 and 6. signal description reset after power up, a master reset operation must be performed by providing a low pulse to rsti and rst2 simultaneously. afterwards, the fifo memories of the idt723622/723632/723642 are reset separately by taking their reset ( rst1 , rst2 ) inputs low for at least four port a clock (clka) and four port b clock (clkb) low-to-high transitions. the reset inputs can switch asynchronously to the clocks. a fifo reset initializes the internal read and write pointers and forces the input ready flag (ira, irb) low, the output ready flag (ora, orb) low, the almost-empty flag ( aea , aeb ) low, and the almost- full flag ( afa , afb ) high. resetting a fifo also forces the mailbox flag ( mbf1 , mbf2 ) of the parallel mailbox register high. after a flfo is reset, its input ready flag is set high after two clock cycles to begin normal operation. a low-to-high transition on a flfo reset ( rst1 , rst2 ) input latches the value of the flag select (fs0, fs1) inputs for choosing the almost-full and almost-empty offset programming method (for details see table 1, flag programming and the almost-empty flag and almost-full flag offset programming section that follows). the relevant fifo reset timing diagram can be found in figure 2. almost-empty flag and almost-full flag offset pro- gramming four registers in these devices are used to hold the offset values for the almost-empty and almost-full flags. the port b almost-empty flag ( aeb ) offset register is labeled x1 and the port a almost-empty flag ( aea ) offset register is labeled x2. the port a almost-full flag ( afa ) offset register is labeled y1 and the port b almost-full flag ( afb ) offset register is labeled y2. the index of each register name corresponds to its fifo number. the offset registers can be loaded with preset values during the reset of a fifo or they can be programmed from port a (see table 1). ? preset values to load the fifo's almost-empty flag and almost-full flag offset registers with one of the three preset values listed in table 1, at least one of the flag select inputs must be high during the low-to-high transition of its reset input. for example, to load the preset value of 64 into x1 and y1, fs0 and fs1 must be high when flfo1 reset ( rst1 ) returns high. flag offset registers associated with fifo2 are loaded with one of the preset values in the same way with fifo2 reset ( rst2 ) toggled simultaneously with fifo1 reset ( rst1 ). for preset value loading timing diagram, see figure 2. fs1 fs0 rst1 rst2 x1 and y1 reglsters(1) x2 and y2 reglsters(2) hh x64 x hh x x64 hl x16 x hl x x16 lh x8 x lh x x8 ll programmed from port a programmed from port a notes: 1. x1 register holds the offset for aeb ; y1 register holds the offset for afa . 2. x2 register holds the offset for aea ; y2 register holds the offset for afb . table 1 flag programming
11 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range the setup and hold time constraints to the port clocks for the port chip selects and write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. if a port enable is low during a clock cycle, the port?s chip select and write/read select may change states during the setup and hold time window of the cycle. when a fifo output ready flag is low, the next word written is automatically sent to the fifo output register automatically by the low-to-high transition of the port clock that sets the output ready flag high. when the output ready flag is high, subsequent data is clocked to the output registers only when a fifo read is selected using the port?s chip select, write/read select, enable, and mailbox select. synchronized fifo flags each fifo is synchronized to its port clock through at least two flip-flop stages. this is done to improve flag-signal reliability by reducing the probability of metastable events when clka and clkb operate asynchro- nously to one another. ora, aea , ira, and afa are synchronized to clka. orb, aeb , irb, and afb are synchronized to clkb. tables 4 and 5 show the relationship of each port flag to fifo1 and fifo2. output ready flags (ora, orb) the output ready flag of a fifo is synchronized to the port clock that reads data from its array. when the output ready flag is high, new data is present in the fifo output register. when the output ready flag is low, the previous data word is present in the fifo output register and attempted fifo reads are ignored. a fifo read pointer is incremented each time a new word is clocked to its output register. the state machine that controls an output ready flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is empty, empty+1, or empty+2. from the time a word is written to a fifo, it can be shifted to the fifo output register in a minimum of three cycles of the output ready flag synchronizing clock. therefore, an output ready flag is low if a word in memory is the next data to be sent to the flfo output register and three cycles of the port clock that reads data from the fifo have not elapsed since the time the word was written. the output ready flag of the fifo remains low until the third low-to-high transition of the synchronizing clock occurs, simultaneously forcing the output ready flag high and shifting the word to the fifo output register. a low-to-high transition on an output ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time t skew1 or greater after the write. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figures 8 and 9 for ora and orb timing diagrams). input ready flags (ira, irb) the input ready flag of a flfo is synchronized to the port clock that writes data to its array. when the input ready flag is high, a memory location is free in the fifo to receive new data. no memory locations are free when the input ready flag is low and attempted writes to the fifo are ignored. each time a word is written to a fifo, its write pointer is incremented. the state machine that controls an input ready flag monitors a write pointer and read pointer comparator that indicates when the flfo memory status is full, full-1, or csb w /rb enb mbb clkb data b (b0-b35) i/o port function h x x x x high-impedance none l l l x x input none llhl input fifo2 write llhh input mail2 write l h l l x output none lhhl output fifo1 read l h l h x output none lhhh output mail1 read (set mbf1 high) table 3 port b enable function table table 2 port a enable function table csa w/ r a ena mba clka data a (a0-a35) i/o port function h x x x x high-impedance none l h l x x input none lhhl input fifo1 write lhhh input mail1 write l l l l x output none llhl output fifo2 read l l l h x output none llhh output mail2 read (set mbf2 high)
12 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range almost-empty state is defined by the contents of register x1 for aeb and register x2 for aea . these registers are loaded with preset values during a fifo reset or programmed from port a (see almost-empty flag and almost-full flag offset programming section). an almost-empty flag is low when its fifo contains x or less words and is high when its fifo contains (x+1) or more words. a data word present in the fifo output register has been read from memory. two low-to-high transitions of the almost-empty flag synchronizing clock are required after a fifo write for its almost-empty flag to reflect the new level of fill. therefore, the almost-full flag of a fifo containing (x+1) or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (x+1) level. an almost-empty flag is set high by the second low-to-high transition of its synchronizing clock after the fifo write that fills memory to the (x+1) level. a low-to-high transition of an almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t skew2 or greater after the write that fills the fifo to (x+1) words. otherwise, the subsequent synchronizing clock cycle may be the first synchro- nization cycle. (see figures 12 and 13). synchronized synchronized number of words in fifo (1,2) to clkb to clka idt723622 (3) idt723632 (3) idt723642 (3) orb aeb afa ira 000llhh 1 to x1 1 to x1 1 to x1 h l h h (x1+1) to [256-(y1+1)] (x1+1) to [512-(y1+1)] (x1+1) to [1,024-(y1+1)] h h h h (256-y1) to 255 (512-y1) to 511 (1,024-y1) to 1,023 h h l h 256 512 1,024 h h l l full-2. from the time a word is read from a fifo, its previous memory location is ready to be written in a minimum of two cycles of the input ready flag synchronizing clock. therefore, an input ready flag is low if less than two cycles of the input ready flag synchronizing clock have elapsed since the next memory write location has been read. the second low-to-high transition on the input ready flag synchronizing clock after the read sets the input ready flag high. a low-to-high transition on an input ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time t skew1 or greater after the read. otherwise, the subsequent clock cycle can be the first synchronization cycle (see figures 10 and 11 for timing diagrams). almost-empty flags ( aea , aeb ) the almost-empty flag of a fifo is synchronized to the port clock that reads data from its array. the state machine that controls an almost-empty flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is almost-empty, almost-empty+1, or almost-empty+2. the notes: 1. when a word loaded to an empty fifo is shifted to the output register, its previous fifo memory location is free. 2. data in the output register does not count as a "word in fifo memory". since the first word written to an empty fifo goes unr equested to the output register (no read operation necessary), it is not included in the fifo memory count. 3. x1 is the almost-empty offset for fifo1 used by aeb . y1 is the almost-full offset for fifo1 used by afa . both x1 and y1 are selected during a reset of fifo1 or programmed from port a. synchronized synchronized number of words in fifo (1,2) to clka to clkb idt723622 (3) idt723632 (3) idt723642 (3) ora aea afb irb 000llhh 1 to x2 1 to x2 1 to x2 h l h h (x2+1) to [256-(y2+1)] (x2+1) to [512-(y2+1)] (x2+1) to [1,024-(y2+1)] h h h h (256-y2) to 255 (512-y2) to 511 (1,024-y2) to 1,023 h h l h 256 512 1,024 h h l l notes: 1. when a word loaded to an empty fifo is shifted to the output register, its previous fifo memory location is free. 2. data in the output register does not count as a "word in fifo memory". since the first word written to an empty fifo goes unr equested to the output register (no read operation necessary), it is not included in the fifo memory count. 3. x2 is the almost-empty offset for fifo2 used by aea . y2 is the almost-full offset for fifo2 used by afb . both x2 and y2 are selected during a reset of fifo2 or programmed from port a. table 4 fifo1 flag operation table 5 fifo2 flag operation
13 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range in memory to [256/512/1,024-(y+1)]. otherwise, the subsequent synchroniz- ing clock cycle may be the first synchronization cycle (see figures 14 and 15). mailbox registers each fifo has a 36-bit bypass register to pass command and control information between port a and port b without putting it in queue. the mailbox select (mba, mbb) inputs choose between a mail register and a fifo for a port data transfer operation. a low-to-high transition on clka writes a0-a35 data to the mail1 register when a port a write is selected by csa , w/ r a, and ena and with mba high. a low-to-high transition on clkb writes b0-b35 data to the mail2 register when a port b write is selected by csb , w / rb, and enb and with mbb high. writing data to a mail register sets its corresponding flag ( mbf1 or mbf2 ) low. attempted writes to a mail register are ignored while the mail flag is low. when data outputs of a port are active, the data on the bus comes from the fifo output register when the port mailbox select input is low and from the mail register when the port-mailbox select input is high. the mail1 register flag ( mbf1 ) is set high by a low-to-high transition on clkb when a port b read is selected by csb , w /rb, and enb and with mbb high. the mail2 register flag ( mbf2 ) is set high by a low-to-high transition on clka when a port a read is selected by csa , w/ r a, and ena and with mba high. the data in a mail register remains intact after it is read and changes only when new data is written to the register. for mail register and mail register flag timing diagrams, see figure 16 and 17. almost-full flags ( afa , afb ) the almost-full flag of a fifo is synchronized to the port clock that writes data to its array. the state machine that controls an almost-full flag monitors a write pointer and read pointer comparator that indicates when the fifo memory status is almost-full, almost-full-1, or almost-full-2. the almost-full state is defined by the contents of register y1 for afa and register y2 for afb . these registers are loaded with preset values during a flfo reset or programmed from port a (see almost-empty flag and almost-full flag offset programming section). an almost-full flag is low when the number of words in its fifo is greater than or equal to (256-y), (512-y), or (1,024-y) for the idt723622, idt723632, or idt723642 respectively. an almost-full flag is high when the number of words in its fifo is less than or equal to [256-(y+1)], [512-(y+1)], or [1,024-(y+1)] for the idt723622, idt723632, or idt723642 respectively. note that a data word present in the fifo output register has been read from memory. two low-to-high transitions of the almost-full flag synchronizing clock are required after a fifo read for its almost-full flag to reflect the new level of fill. therefore, the almost-full flag of a fifo containing [256/512/1,024-(y+1)] or less words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [256/ 512/1,024-(y+1)]. an almost-full flag is set high by the second low-to-high transition of its synchronizing clock after the fifo read that reduces the number of words in memory to [256/512/1,024-(y+1)]. a low-to-high transition of an almost-full flag synchronizing clock begins the first synchronization cycle if it occurs at time t skew2 or greater after the read that reduces the number of words
14 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range note: 1. fifo2 is reset in the same manner to load x2 and y2 with a preset value. figure 2. fifo1 reset and loading x1 and y1 with a preset value of eight (1) notes: 1. t skew1 is the minimum time between the rising clka edge and a rising clkb edge for irb to transition high in the next cycle. if the time between the rising edge of clka and rising edge of clkb is less than t skew1 , then irb may transition high one clkb cycle later than shown. 2. csa = low, w/ r a = high, mba = low. it is not necessary to program offset register on consecutive clock cycles. figure 3. parallel programming of the almost-full flag and almost-empty flag offset values after reset 3022 drw 05 clka rst1, rst2 ira clkb irb a0 - a35 fs1,fs0 ena t fss t fsh t pir t enh t ens2 t skew1 t ds t dh t pir 4 0,0 afa offset (y1) aeb offset (x1) afb offset (y2) aea offset (x2) first word to fifo1 1 2 (1) 12 clka rst1 ira aeb afa mbf1 clkb orb fs1,fs0 3022 drw 04 t rsts t rsth t fsh t fss t pir t pir t por t rsf 0,1 t rsf t rsf
15 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range figure 5. port b write cycle timing for fifo2 note: 1. written to fifo1. figure 4. port a write cycle timing for fifo1 note: 1. written to fifo2. 3022 drw 07 clkb irb enb b0 - b35 mbb csb w /rb t clk t clkh t clkl t enh t enh t enh t enh t dh w1 (1) w2 (1) t ds t ens1 t enh t enh no operation t ens1 t ens2 t ens2 t ens2 t ens2 high 3022 drw 06 clka ira ena a0 - a35 mba csa w/ r a t clkh t clkl t clk t ens1 t ds t enh t enh t enh t enh t dh w1 (1) w2 (1) t enh t enh no operation high t ens1 t ens2 t ens2 t ens2 t ens2
16 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range note: 1. read from fifo1. figure 6. port b read cycle timing for fifo1 figure 7. port a read cycle timing for fifo2 note: 1. read from fifo2. 3022 drw 09 clka ora ena a0 - a35 mba csa w/ r a t clk t clkh t clkl t dmv t en t a t a t enh t enh t ens2 t enh w1 w2 w3 (1) (1) (1) t dis no operation t ens2 t ens2 3022 drw 08 clkb orb enb b0 - b35 mbb csb w /rb t clk t clkh t clkl t ens2 t a t mdv t en t a t enh t enh w1 w2 w3 (1) (1) (1) t enh t dis no operation t ens2 t ens2 high
17 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range note: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for orb to transition high and to clock the next word to the fifo1 output register in three clkb cycles. if the time between the rising clka edge and rising clkb edge is less than t skew1 , then the transition of orb high and load of the first word to the output register may occur one clkb cycle later than shown. figure 8. orb flag timing and first data word fall through when fifo1 is empty csa w r a mba ira a0 - a35 clkb orb ena clka 12 3 t clkh t clkl t clk t ens2 t ens2 t enh t enh t ds t dh t skew1 t clk t clkl t por fifo1 empty low high t clkh w1 high (1) t por t a t ens2 t enh w1 4660 drw 10 old data in fifo1 output register low csb high low mbb w /rb enb b0 - b35
18 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range note: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ora to transition high and to clock the next word to the fifo2 output register in three clka cycles. if the time between the rising clkb edge and rising clka edge is less than t skew1 , then the transition of ora high and load of the first word to the output register may occur one clka cycle later than shown. figure 9. ora flag timing and first data word fall through when fifo2 is empty csb w /rb mbb irb b0 - b35 clka ora csa w/ r a mba enb ena a0-a35 clkb 3022 drw 11 12 3 t clkh t clkl t clk t ens2 t ens2 t enh t enh t ds t dh t skew1 t clk t clkh t por t por t ens2 t enh t a old data in fifo2 output register w1 fifo2 empty t clkl low low low low low high w1 (1)
19 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range note: 1. t skew1 is the minimum time between a rising clkb edge and a rising clka edge for ira to transition high in the next clka cycle. if t he time between the rising clkb edge and rising clka edge is less than t skew1 , then ira may transition high one clka cycle later than shown. figure 10. ira flag timing and first available write when fifo1 is full csb orb w /rb mbb enb b0 -b35 clkb ira clka csa 3022 drw 12 w/ r a mba 12 t clk t clkh t clkl t ens2 t enh t a t skew1 t clk t clkh t clkl t pir t pir t ens2 t ens2 t ds t enh t enh t dh to fifo1 previous word in fifo1 output register next word from fifo1 low high low high low high (1) fifo1 full ena a0-a35 write
20 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range figure 12. timing for aeb when fifo1 is almost-empty notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for aeb to transition high in the next clkb cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then aeb may transition high one clkb cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = low, mba = low), fifo1 read ( csb = low, w /rb = high, mbb = low). data in the fifo1 output register has been read from the fifo. note: 1. t skew1 is the minimum time between a rising clka edge and a rising clkb edge for irb to transition high in the next clkb cycle. if t he time between the rising clka edge and rising clkb edge is less than t skew1 , then irb may transition high one clkb cycle later than shown. figure 11. irb flag timing and first available write when fifo2 is full aeb clka enb 3022 drw 14 ena clkb 2 1 t ens2 t enh t skew2 t pae t pae t ens2 t enh x1 words in fifo1 (x1+1) words in fifo1 (1) csa ora w/ r a mba ena a0 -a35 clka irb clkb csb w/ rb mbb 12 t clk t clkh t clkl t ens2 t enh t a t skew1 t clk t clkh t clkl t pir t ens2 t ens2 previous word in fifo2 output register next word from fifo2 fifo2 full low low low high low low (1) t pir t ds t enh t enh t dh enb b0 - b35 to fifo2 wriite 3022 drw 13
21 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for aea to transition high in the next clka cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then aea may transition high one clka cycle later than shown. 2. fifo2 write ( csb = low, w /rb = low, mbb = low), fifo2 read ( csa = low, w/ r a = low, mba = low). data in the fifo2 output register has been read from the fifo. figure 13. timing for aea when fifo2 is almost-empty notes: 1. t skew2 is the minimum time between a rising clka edge and a rising clkb edge for afa to transition high in the next clka cycle. if the time between the rising clka edge and rising clkb edge is less than t skew2 , then afa may transition high one clka cycle later than shown. 2. fifo1 write ( csa = low, w/ r a = high, mba = low), fifo1 read ( csb = low, w /rb = high, mbb = low). data in the fifo1 output register has been read from the fifo. 3. d = maximum fifo depth = 256 for the idt723622, 512 for the idt723632, 1,024 for the idt723642. figure 14. timing for afa when fifo1 is almost-full afa clka enb 3022 drw 16 ena clkb 12 t skew2 t ens2 t enh t paf t ens2 t enh t paf [d-(y1+1)] words in fifo1 (d-y1) words in fifo1 (1) aea clkb ena 3022 drw 15 enb clka 2 1 t en2s t enh t skew2 t pae t pae t ens2 t enh (x2+1) words in fifo2 x2 words in fifo2 (1)
22 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range notes: 1. t skew2 is the minimum time between a rising clkb edge and a rising clka edge for afb to transition high in the next clkb cycle. if the time between the rising clkb edge and rising clka edge is less than t skew2 , then afb may transition high one clkb cycle later than shown. 2. fifo2 write ( csb = low, w /rb = low, mbb = low), fifo2 read ( csa = low, w/ r a = low, mba = low). data in the fifo2 output register has been read from the fifo. 3. d = maximum fifo depth = 256 for the idt723622, 512 for the idt723632, 1,024 for the idt723642. figure 15. timing for afb when fifo2 is almost-full figure 16. timing for mail1 register and mbf1 flag 3022 drw 18 clka ena a0 - a35 mba csa w/ r a clkb mbf1 csb mbb enb b0 - b35 w /rb w1 t ens1 t enh t ds t dh t pmf t pmf t en t mdv t pmr t ens2 t enh t dis w1 (remains valid in mail1 register after read) fifo1 output register t ens1 t ens2 t ens2 t enh t enh t enh afb clkb ena 3022 drw 17 enb clka 12 t skew2 t ens2 t enh t paf t ens2 t enh t paf [d-(y2+1)] words in fifo2 (d-y2) words in fifo2 (1)
23 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range figure 17. timing for mail2 register and mbf2 flag 3022 drw19 clkb enb b0-b35 mbb csb w /rb clka mbf2 csa mba ena a0-a35 w/ r a w1 t enh t dh t pmf t pmf t ens2 t enh t dis t en t mdv t pmr fifo2 output register w1 (remains valid in mail 2 register after read) t enh t enh t enh t ds t ens1 t ens1 t ens2 t ens2
24 idt723622/723632/723642 cmos syncbififo? 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 commercial temperature range figure 18. load circuit and voltage waveforms note: 1. includes probe and jig capacitance. 3022 drw 20 parameter measurement information from output under test 30 pf 1.1 k ? 5 v 680 ? propagation delay load circuit 3 v gnd timing input data, enable input gnd 3 v 1.5 v 1.5 v voltage waveforms setup and hold times voltage waveforms pulse durations voltage waveforms enable and disable times voltage waveforms propagation delay times 3 v gnd gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v t w output enable low-level output high-level output 3 v ol gnd 3 v 1.5 v 1.5 v 1.5 v 1.5 v oh ov gnd oh ol 1.5 v 1.5 v 1.5 v 1.5 v input in-phase output high-level input low-level input v v v v 1.5 v 3 v t s t h t plz t phz t pzl t pzh t pd t pd (1)
25 corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-360-1753 san jose, ca 95138 fax: 408-284-2775 email: fifohelp@ idt.com www.idt.com ordering information note: 1. industrial temperature range is available by special order. blank 3022 drw 21 commercial (0 c to +70 c) xxxxxx idt device type xxx x x power speed package process/ temperature range commercial only clock cycle time (t clk ) speed in nanoseconds pf pqf 12 15 l 723622 723632 723642 thin quad flat pack (tqfp, pn120-1) plastic quad flat pack (pqfp, pq132-1) low power 256 x 36 x 2 ? syncbififo ? 512 x 36 x 2 ? syncbififo ? 1,024 x 36 x 2 ? syncbififo ? datasheet document history 10/04/2000 pgs. 1 through 25, except pages 3 and 5. 03/21/2001 pgs. 6 and 7. 08/01/2001 pgs. 1, 6, 8, 9 and 25. 12/18/2001 pg. 23.

▲Up To Search▲

Price & Availability of 723622L12PQF

	To Download 723622L12PQF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .